1. Field of the invention
The present invention relates to a watch-dog timer circuit to monitor both the uncontrollable operation of a CPU and the stop of system clock pulse oscillation, and relates to a microcomputer equipped with the watch-dog timer circuit.
2. Description of Related Art
FIG. 1 is a block circuit diagram illustrative of the construction of a microcomputer equipped with the conventional watch-dog timer circuit being incorporated therein. The microcomputer is equipped with a watch-dog timer 33 which, when a CPU 29 runs out of control due to a certain cause during execution of a program which has been read from a memory 32 via a system bus 30, detects the uncontrollable operation of the CPU 29 and sends to a reset circuit a reset request signal D thereby to reset the system.
The watch-dog timer 33 is equipped with an up-count type counter 1 which counts pulses of system clock signal P generated from a waveform oscillated by an oscillator circuit 28, and is programmed so that a clear signal C is input from the CPU 29 to clear the count before the count of the counter 1 overflows. Therefore, when the CPU 29 runs out of control to cause the counter i to overflow, the watch-dog timer circuit outputs the reset request signal D to the reset circuit. 31 to request it to reset the system. Upon receipt of the reset request signal D, the reset circuit 31 outputs a reset signal R to the CPU 29 and the input/output port 35 to reset the CPU 29 and the input/output port 35. The counter 1 may also be of down-cogent type.
However, the conventional watch-dog timer 33 has a problem of losing the system monitoring function when the oscillator circuit Z8 stops the oscillation due to an oscillation failure or an uncontrollable operation of the microcomputer, because a system clock signal P which is the counter source of the counter 1 of the watch-dog timer 33 is interrupted thereby to stop counting of the counter 1.
Even if it is attempted to reset by other means than the watch-dog timer 33, resetting operation is disabled when the oscillator circuit 28 has stopped oscillation, because operation of the reset circuit 31 is based on the system clock signal P obtained from the waveform oscillated by the oscillator circuit 28. Consequently, the input/output port 35 cannot be reset and abnormal output continues to be sent, eventually resulting in abnormal output because of stop of the oscillation of the microcomputer. While conflict of signals or the like caused by such an abnormal output may affect the entire system which uses t, he microcomputer, there has been no means of preventing such troubles.